Integrated circuits are often designed using pre-designed Intellectual Property (IP) modules. Such modules define all of part of a function or function within an integrated circuit. The modules are often supplied as a parameterisable core or as an executable module generator (for example, a Perl, TCL, or Java executable that generates a configured HDL (Hardware Description language) instance of the IP module). Ports on a module either provide a complete set of connections as specified by the bus/communication protocol, or are configured by the designer to implement only the subset of features needed for the application.
In one example of a system design tool, the Altera NIOS™ System Builder uses a proprietor file format (labelled “.ptf”) file to describe connections on an IP module. Each port of the module can be specified as bus slave or as bus master. Other parameters such as module base address, port width, and port name on the component can be specified. When incorporated into a design, the module description is used to construct a “bus module” which has appropriate connections to the module itself.
Configuring each module in a system by hand is a time consuming and error prone activity. As each module is unaware of the requirements and capabilities of the other modules to which it is connected it is impossible to remove unused services or make other optimisations in an efficient way. Indeed, with anything other than the most trivial of systems, the task is practically impossible.
In addition, new bus protocols cannot be specified without modifying the design tool significantly.
Accordingly, it is desirable to provide a design tool and method which can overcome these problems.